1. Field of the Invention
The present invention relates to the techniques for improving the overvoltage protection function in the insulated gate type power devices which are represented by insulated gate bipolar transistors (hereinafter referred to as "IGBT").
2. Description of the Background Art
For power devices such as power transistors represented by IGBTs, it is desirable to improve their breakdown voltage and current-carrying capacities so that they can be used in high voltages and high currents. Particularly, elements should be designed with a sufficient margin for breakdown voltage. This is because when power devices are used actually in a circuit, an overvoltage might be applied by such as the fluctuations of power supply voltage, the regeneration of load power, and the induced electromotive force (spike voltage) which occur in wire because of a prompt current change in switching and inductance of the wire. As a result, a breakdown may occur at P-type base junction (in the case of N-channel type IGBTs) of the cell of IGBT, and a breakdown current flows so that the thyristor being parasitic on the IGBT latches up, leading to the breakdown of the IGBT.
Adding a sufficient margin for breakdown voltage, however, raises manufacturing cost and power loss. Hence, there has been discussed to find a reasonable level.
As one answer to this problem, there is a method (called "active clamp") in which when a high voltage approaching a breakdown voltage is applied between the main electrodes (between the collector and emitter) of a power transistor, a voltage to be applied to the control electrode (i.e., gate) of the power transistor is controlled to drive the power transistor to enter ON state (hereinafter referred to as "ON drive"). With this method, the impedance between the main electrodes is lowered, which suppresses an increase in the voltage applied thereto, preventing a breakdown current from flowing to the P-type base junction.
In utilizing "active clamp," there are required means for detecting that the voltage between the main electrodes has approached a breakdown voltage, and means for driving a power transistor to enter ON drive with a control electrode. The detection of voltage between the main electrodes has been conventionally made by connecting an avalanche diode having a high breakdown voltage which is provided apart from (i.e., outside of) a power transistor, between the collector and gate of the power transistor. The breakdown voltage of the avalanche diode is set to be slightly lower than that of a power transistor to be protected. Therefore, in the event of breakdown of the avalanche diode, the gate of the power transistor is charged with the charge carried in its breakdown current, thereby increasing the gate voltage. This allows a power transistor to enter ON state immediately before the power transistor leads to its breakdown. In order to prevent the forward current that flows to the avalanche diode at the normal on-state drive, a diode is connected in series with the avalanche diode in the opposite direction.
With the technique of providing an avalanche diode apart from a power transistor as described, however, it is necessary to adjust the breakdown voltage of the avalanche diode and that of the power transistor in separate manufacturing steps so that they have a proper relation. Accordingly, this technique is not suitable for production in quantity and also increases cost and the number of parts.
Therefore, incorporating an avalanche diode in a power transistor has been proposed. Both share several diffusion steps and lithography steps, thus being suitable for mass production.
FIG. 8 is a cross-sectional view that schematically shows the configuration of N-channel IGBT 200 of the planar gate type in which an avalanche diode is incorporated. On a first major surface of N-type base region 1 (the major surface located above in FIG. 8) having a low impurity concentration, P-type diffused base regions 2 are selectively formed at specific intervals. N-type diffused emitter regions 3 having a high impurity concentration, which have been selectively formed in the first major surface, are provided in the P-type diffused base region 2. In the P-type diffused base region 2, the region which is sandwiched between the N-type base region 1 and the N-type diffused emitter region 3, and also is exposed to the first major surface (hereinafter the region is referred to as "channel region") is covered with, for example, a gate oxide film 6 formed by a silicon oxide film. Internal gate electrodes 7 which are formed by, for example, polysilicon having a high impurity concentration is opposed to the channel region through the gate oxide film 6. All the internal gate electrodes 7 are connected in common to a gate terminal.
The P-type diffused lease region 2 except for the channel region and the N-type diffused emitter region 3, are connected to an emitter terminal (Emitter), through an external emitter electrode 9 in the first major surface.
On a second major surface of the N-type base region 1 (i.e., the major surface located under in FIG. 8), N-type buffer region 4 having a high impurity concentration, P-type region 5 having a higher impurity concentration than the N-type buffer region 4, and an external collector electrode 10, are stacked in this order. A collector terminal (Collector) is connected to the external collector electrode 10.
Aside from the P-type diffused base region 2, at least one P-type avalanche diode diffused region 8 is formed, which is connected through an electrode 93 to the anode of a diode D0 provided outside, on the first major surface of N type base region 1. The cathode of the diode D0 is connected to a gate terminal. That is, to an avalanche diode Da formed by the N-type base region 1 and the avalanche diode diffused region 8, the diode D0 is connected in series in the opposite direction to prevent the forward current flow, as described earlier.
Here, the avalanche diode diffused region 8 can have a greater curvature in shape than that of the P-type diffused base region 2 by making the former shallower than the latter. Therefore, the electric field of the backward bias in the avalanche diode Da can be greater than that in the boundary between the N-type base region 1 and the P-type diffused base region 2.
The following description will be given of the cases where a biasing is made in N-channel IGBT 200 so that the potential of a gate terminal is lower than that of an emitter terminal, by using a gate driving power supply (not shown) and an appropriate current limiting resistor (not shown). In this case, the potential of a channel region is lower than that of P-type diffused base region 2 except for the channel region, causing no depletion in the channel region. Accordingly, even when the potential of a collector terminal is higher than that of the emitter terminal, hardly or no current flows between the two, to enter OFF state. In this state, if the voltage of the collector terminal is increased, a depletion layer expands into the N-type base region 1 to strengthen the electric field in the boundary between the N-type base region 1 and the N-type diffused base region 2.
When this electric field is higher than the critical electric field of silicon (approximately 2.times.10.sup.5 V/cm), the ionization by collision of carriers becomes violent rapidly so that IGBT exhibits breakdown characteristics. In the N-channel IGBT 200 with an avalanche diode Da, however, at a potential difference lower than that in the breakdown of the N-channel IGBT 200, the avalanche diode Da receives the critical electric field to cause a breakdown. Then, by the breakdown of the avalanche diode Da, the current flows to the gate driving power supply through the diode D0 and the current limiting resistor. As a result, the voltage generated in the current limiting resistor raises the potential of the gate terminal, thereby the potential of the channel region increases, and an inversion layer (channel) is generated there. Since the current flows between the emitter terminal and collector terminal through the channel, the impedance between the main electrodes is lowered to relax the overvoltage applied therebetween, so that the electric field in the boundary between the N-type base region 1 and the P-type diffused base region 2 is also relaxed to avoid a breakdown at this boundary.
It is assumed that the above operation is basically the same for the cases where the N-channel IGBT 200 is in a transient operation state, and it is also possible to suppress the spike voltage in the turn-off operation. The configuration of N-channel IGBT 200 is presented, for example, by Tomoyuki Yamazaki et al., AVALANCHE SECURED IGBT (1992 National Convention Record I.E.E. Japan vol. 5, pp 5-16).
In the above technique, however, the following problems remain. A first problem is that an avalanche diode Da cannot be formed in P-type diffused base region 2 whereat a channel region will be formed. Therefore, it is necessary to form an avalanche diode Da apart from the array of P-type diffused base regions 2 that are repetitively formed at specific pitches. As a result, the vicinity of the avalanche diode Da differs in electric field distribution from the vicinity of the array of the P-type diffused base regions 2. Particularly, the breakdown occurred in the state where carriers exist in a high density in N-type base region 1 could not be detected by the avalanche diode Da (that is, the avalanche diode Da causes no breakdown before a breakdown occurs between the N-type base region 1 and the P-type diffused base region 2 in such a state).
A second problem relates to the outflow of excess carriers stored in N-type base region 1. Such excess carriers flow out during turn-off operation, through not only P-type diffused base region 2 but an avalanche diode Da. This may raise the potential of a gate terminal to retard the turn-off operation.
A third problem relates to the possibility that if OFF state is obtained with the potential of a gate terminal lower than that of an emitter terminal a diode D0 may enter the conductive state, and then the reverse bias is applied to an avalanche diode Da, so that the breakdown voltage of the avalanche diode Da may be virtually lowered.